An impurity in a semiconductor which accepts electrons excited from the valence band, leading to hole conduction.
Active Si layer
Silicon layer on top of the buried oxide (BOX) in SOI substrates.
Ability of materials to stick (adhere) to each other.
Adhesion layer
Material used to improve adhesion of materials, typically photo resist to the substrate in a photo lithographic process. Some metals are also used to promote adhesion of subsequent layers.
Amorphous Si, a-Si
Non-crystalline thin-film silicon having no long-range crystallography order; inferior electrical characteristics as compared to single-crystal and poly Si but cheaper and easier to manufacture; used primarily to fabricate solar cells.
Angstrom, Å
Unit of length commonly used in semiconductor industry, though it is not recognized as a standard international unit; 1 Å = 10-8cm = 10-4 micrometer = 0.1 nm; the dimensions of a typical atoms.
Exhibiting physical properties in differing crystallography directions.
Anisotropic Etch
A selective etch which exhibits an accelerated etch rate along specific crystallography directions.
Acid Waste Neutralization


Batch process
Process in which many wafers are processed simultaneously, as opposed to a single wafer process.
Semiconductor device fabrication technology which produces transistors that use both holes and electrons as charge carriers.
1. A device made of high purity temperature resistant materials such as fused silica, quartz, poly Si, or SiC designed to hold many semiconductor wafers during thermal or other processes; 2. A device designed to simultaneously contain source material during evaporation while at the same time heating the source to its melting point; made of highly conductive, temperature-resistant material through which current is passed.
Bonded SOI
SOI substrate formed by bonding two silicon wafers with oxidized surfaces such that one wafer is formed with an oxide layer sandwiched between two layers of Si; one wafer is subsequently polished down to a specified thickness to form an active layer where devices will be fabricated.
Element from group III of the periodic table; acts as an acceptor in silicon; Boron is the only p-type dopant used in silicon device manufacturing.
Concavity, curvature, or deformation of the wafer centerline independent of any thickness variation present.
Buried Oxide in SOI substrates; the layer between wafers.


Chemical Mechanical Polishing, CMP
A process for removal of surface material from the wafer which uses chemical and mechanical actions to achieve a mirror-like surface for subsequent processing.
Chuck Mark
Any physical mark on either surface of a wafer caused by robotic end effecter, chuck, or wand.
Clean Room
Enclosed ultra-clean space necessary for semiconductor manufacturing. Airborne particles are removed from the space to specified minimum levels, room temperature and humidity are strictly controlled; clean rooms are rated and range from Class 1 to Class 10,000. The number corresponds to the number of particles per cubic foot.
Cleavage Plane
A crystallography preferred fracture plane.
Compound Semiconductor
Synthetic semiconductor formed using two or more elements mainly from groups II through VI of the periodic table; compound semiconductors do not appear in nature.
A measure of the ease with which charge carriers flow in a material; the reciprocal of resistivity.
Solid featuring periodic spatial arrangement of atoms throughout the entire piece of material.
Crystal Defects
Departure from the ideal arrangement of atoms in a crystal.
Crystal Pulling
Process in which single-crystal seed is slowly withdrawn from the melt and material condenses at the liquid-solid interface gradually forming a rod-shaped piece of single-crystal material. Crystal pulling is the foundation of the Czochralski (CZ) single-crystal growth technique.
Czochralski Crystal Growth, CZ
Process utilizing crystal pulling to obtain single-crystal solids; the most common method for obtaining large diameter semiconductor wafers (e.g. 300mm Si wafers); desired conductivity type and doping level is accomplished by adding dopants to molten material. Wafers used in high-end Si microelectronics are almost uniquely CZ grown.


Very small voids in Si formed by agglomeration of vacancies.
Denuded Zone
A very thin region on a semiconductor substrate surface cleared from contaminants and/or defects by gettering.
Process of cutting semiconductor wafer into individual chips each containing a complete semiconductor device. Large diameter wafer dicing is carried out by partially cutting the wafer along preferred crystallography planes using high precision saw with ultra-thin diamond blade.
A single piece of semiconductor containing entire integrated circuit which has not yet been packaged; a chip.
Diffusion layer
A region of opposite conductivity type formed near the surface of a semiconductor crystal as a result of the introduction of impurities into the silicon crystal by means of solid state diffusion.
A shallow depression with gently sloping sides that exhibits a concave, spheroidal shape and is visible to the unaided eye under proper lighting conditions.
An impurity or imperfection in a semiconductor which donates electrons to the conduction band, leading to electron conduction.
Addition of specific impurities to a semiconductor to control the electrical resistivity.


Elemental Semiconductor
A single element semiconductor from group IV of the periodic table; Si, Ge, C, Sn.
EPI Layer
The term epitaxial comes from the Greek word meaning 'arranged upon.' In semiconductor technology, it refers to the single crystalline structure of the film. The structure comes about when silicon atoms are deposited on a bare silicon wafer in a CVD reactor. When the chemical reactants are controlled and the system parameters are set correctly, the depositing atoms arrive at the wafer surface with sufficient energy to move around on the surface and orient themselves to the crystal arrangement of the wafer atoms. Thus an epitaxial film deposited on a <111> oriented wafer will take on a <111> orientation.
Epitaxial Layer
A layer grown in the course of epitaxy.
A process by which a thin "epitaxial" layer of single-crystal material is deposited on single-crystal substrate; epitaxial growth occurs in such way that the crystallography structure of the substrate is reproduced in the growing material; also crystalline defects of the substrate are reproduced in the growing material. Although crystallography structure of the substrate is reproduced, doping levels and the conductivity type of an epitaxial layer is controlled independently of the substrate; e.g. the epitaxial layer can be made more pure chemically than the substrate.
A solution, a mixture of solutions, or a mixture of gases that attacks the surfaces of a film or substrate, removing material either selectively or non-selectively.
The common method used to deposit thin-film materials; material to be deposited is heated in a vacuum (10-6 - 10-7 Torr range) until it melts and starts evaporating; this vapor condenses on a cooler substrate inside the evaporation chamber forming very smooth and uniform thin films; not suitable for high melting point materials; PVD method of thin film formation.
External, extrinsic gettering
The process in which gettering of contaminants and defects in a semiconductor wafer is accomplished by stressing its back surface (by inducing damage or depositing material featuring different than semiconductor thermal expansion coefficient) and then thermally treating the wafer; contaminants and/or defects are relocated toward back surface and away from the front surface where semiconductor devices can be formed.


A portion of the periphery of a circular wafer that has been removed to a chord.
For wafer surfaces, the deviation of the front surface, expressed in TIR or maximum FPD, relative to a specified reference plane when the back surface of the wafer is ideally flat, as when pulled down by a vacuum onto an ideally clean, flat chuck.
Float-zone Crystal Growth, FZ
The method used to form single crystal semiconductor substrates (alternative to CZ). Poly crystalline material is converted into single-crystal by locally melting the plane where a single crystal seed is contacting the poly crystalline material. Used to make very pure, high resistance Si wafers. Does not allow as large wafers (< 200mm) as CZ does. Radial distribution of dopant in FZ wafer is not as uniform as in CZ wafer.
Focal plane
The plane perpendicular to the optical axis of an imaging system which contains the focal point of the imaging system.


Process which moves contaminants and/or defects in a semiconductor away from its top surface into its bulk and traps them there, creating a denuded zone.
Global Flatness
The TIR or the maximum FPD relative to a specified reference plane within the FQA.


Non-localized light scattering resulting from the surface topography (micro roughness) or from dense concentrations of surface or near-surface imperfections.
Hexamethyldisilizane; improves adhesion of photoresist to the surface of a wafer; especially designed for adhesion of photoresist to SiO2; deposited on wafer surface immediately prior to deposition of resist.


A cylinder or rectangular solid of poly crystalline or single crystal silicon, generally of slightly irregular dimensions.
Intrinsic Gettering
Process in which gettering of contaminants and/or defects in a semiconductor is accomplished (without any physical interactions with the wafer) by a series of heat treatments.


Jeida Flat
Japanese standard for major flat length (47.5 +/- 2.5mm)


Line defect
Localized light-scatter
An isolated feature, such as particle or pit, on or in a wafer surface, resulting in increased light scattering intensity relative to that of the surrounding wafer surface; sometimes called a light point defect.


Minority Carrier
Type of charge carrier constituting less than one half the total charge carrier concentration.
Monitor Grade
Used mostly for particle monitors.


Nanometer, nm
Unit of length commonly used in semiconductor industry; one billionth of a meter, 10-9m [nm]; terms such as microchip and micro technology are being replaced with nanochip and nanotechnology.
An intentionally fabricated indent of specified shape and dimensions oriented such that the diameter passing through the center of the notch is parallel with a specified low index crystal direction.
N-type Semiconductor
Semiconductor in which the concentration of electrons is much higher than the concentration of holes (p>>n); electrons are majority carriers and dominate conductivity.


Oxygen in silicon
Oxygen finds its way into silicon during the Czochralski single-crystal growth process; in moderate concentration (below 1017cm3) oxygen improves mechanical properties of a silicon wafer; excess oxygen acts as a n-type dopant in silicon.


A small, discrete piece of foreign material or silicon not connected crystallography to the wafer.
Physical Vapor Deposition, PVD
Deposition of thin film occurs through physical transfer of material (e.g. thermal evaporation and sputtering) from the source to the substrate; the chemical composition of deposited material is not altered in the process.
Planar Defect
Also known as area defect; basically an array of dislocations, e.g. grain boundaries, stacking faults.
Point Defect
A localized crystal defect such as lattice vacancy, interstitial atom, or substitutional impurity. Contrast with light point defect.
Process applied to either reduce roughness of the wafer surface or to remove excess material from the surface; typically polishing is a mechanical-chemical process using chemically reactive slurry.
Poly Crystalline Material, Poly
Many (often) small single-crystal regions are randomly connected to form a solid; size of regions varies depending on the material and the method of its formation. Heavily-doped poly Si is commonly used as a gate contact in silicon MOS and CMOS devices.
Primary Flat
The flat of longest length on the wafer, oriented such that the chord is parallel with a specified low index crystal plane; major flat.
Prime Grade
The highest grade of a silicon wafer. SEMI indicates the bulk, surface, and physical properties required to label silicon wafers as "Prime Wafers". Used to manufacture devices, etc., best grade has tight mechanical and electrical properties.
P-type Semiconductor
Semiconductor in which the concentration of holes is much higher than the concentration of electrons (n>>p); holes are majority carriers and dominate conductivity.


Single-crystal SiO2.


RCA Clean
Is a standard set of wafer cleaning steps which needs to be performed before high temp processing steps (oxidation, diffusion, CVD) of silicon wafers in semiconductor manufacturing. RCA cleaning includes RCA-1 and RCA-2 cleaning procedures. RCA-1 involves removal of organic contaminants, while RCA-2 involves removal of metallic contaminants.
Reclaim Grade
A lower quality wafer that has been used in manufacturing and then reclaimed (etched or polished) and subsequently used again in manufacturing.
Resistivity (electrical)
The measure of difficulty with which charged carriers flow through a material; the reciprocal of conductivity.
The more narrowly spaced components of surface texture.


Single-crystal Al2O3; can be synthesized and processed into various shapes; highly resistant chemically; transparent to UV radiation.
1st cleaning bath in standard RCA Clean sequence, NH4OH/H2O2/H2O solution designed to remove particles from Si surface.
2nd cleaning bath in standard RCA Clean sequence, HCl/H2O2/H2O solution designed to remove metals from the Si surface.
Secondary Flat
Flat of length shorter than the primary orientation flat, whose position with respect to the primary orientation flat identifies the type and orientation of the wafer; minor flat.
Seed Crystal
Single crystal material used in crystal growing to set a pattern for the growth of material in which this pattern is reproduced.
The most common semiconductor, atomic number 14, energy gap Eg=1.12 eV-indirect band gap; crystal structure-diamond, lattice constant 0.543 nm, atomic concentration 5x1022 atoms/cm, index of refraction 3.42, density2.33 g/cm3, dielectric constant 11.7, intrinsic carrier concentration 1.02x1010cm-3, mobility of electrons and holes at 300º K: 1450 and 500 cm2/V-s, thermal conductivity 1.31 W/cmºC, thermal expansion coefficient 2.6x10-6 ºC-1, melting point 1414ºC; excellent mechanical properties (MEMS applications); single crystal Si can be processed into wafers up to 300mm in diameter.
Separation by Implantation of Oxygen. Oxygen ions re-implanted into Si substrate and form a buried oxide layer. SIMOX is a common technique when building Silicon on Insulator (SOI) wafers.
Single Wafer Process
Only one wafer is processed at the time; tools that are designed specifically for single-wafer processing become more common as wafer diameter increases.
Crystalline solid in which atoms are arranged following specific pattern throughout the entire piece of material; in general, single crystal material features superior electronic and photonic properties as compared to poly crystalline and amorphous materials, but is more difficult to fabricate; all high-end semiconductor electronic and photonic materials are fabricated using single-crystal substrates.
Site Flatness
The TIR or the maximum FPD of the portion of a site which falls within the FQA.
Slice Orientation
The angle between the surface of a slice and the growth plane of the crystal. The most common slice orientations are <100>, <111> and <110>.
Term refers to the process of cutting of the single-crystal ingot into wafers; high precision diamond blades are used.
A liquid containing suspended abrasive component; used for lapping, polishing and grinding of solid surfaces; can be chemically active; key element of CMP processes.
Smart Cut
Process used to fabricate bonded SOI substrates by cleaving the top wafer close to the desired thickness of the active layer. Before bonding, one wafer is implanted with hydrogen to a depth that will determine the thickness of an active layer in the future SOI wafer; following bonding, the wafer is annealed (at ~500ºC) at which time the wafer splits along the plane stressed with implanted hydrogen. The result is a very thin layer of Si forming a SOI substrate.
Silicon-On-Insulator; silicon substrate of choice in future generation CMOS ICs; basically a silicon wafer with a thin layer of oxide (SiO2) buried in it; devices are built into a layer of silicon on top of the buried oxide and are thus electrically isolated from the substrate; SOI substrates provide superior isolation between adjacent devices in an IC; SOI devices have reduced parasitic capacitances.
Silicon-On-Sapphire; special case of SOI where an active Si layer is formed on top of a sapphire substrate (an insulator)by means of epitaxial deposition; due to a slight lattice mismatch between Si and sapphire, Si epitaxial layers larger than the critical thickness have a high defect density.
Sputtering Target
Source material during sputter deposition processes; typically a disc inside the vacuum chamber which is exposed to bombarding ions, knocking source atoms loose and onto samples.
Sputtering, Sputter Deposition
Bombardment of a solid (target) by high energy chemically inert ions (e.g. Ar+); causes ejection of atoms from the target which are then redeposited on the surface of a substrate purposely located in the vicinity of the target; common method of Physical Vapor Deposition of metals and oxides.
Surface Damage
Process related disruption of the crystallography order at the surface of single-crystal semiconductor substrates; typically caused by surface interactions with high energy ions during dry etching and ion implantation.
Surface Roughness
Disruption of the planarity of the semiconductor surface; measured as a difference between highest and deepest surface features; can be as low as 0.06nm or high quality Si wafers with epitaxial layers.


Source material used during evaporation or deposition; in sputtering, typically in the form of high purity disc; in e-Beam evaporation, typically in the form of a crucible. In thermal evaporation, the source material is typically held in a boat which is heated resistively.
Test Grade
A virgin silicon wafer of lower quality than Prime, and used primarily for testing processes. SEMI indicates the bulk, surface, and physical properties required to label silicon wafers as "Test Wafers". Used in research & testing equipment.
Thermal Oxidation, Thermal Oxide
Growth of oxide on the substrate through oxidation of the surface at elevated temperature; thermal oxidation of silicon results in a very high quality oxide, SiO2; most other semiconductors do not form device quality thermal oxide, hence, "thermal oxidation" is almost synonymous with "thermal oxidation of silicon".
Total Indicator Reading (TIR)
The smallest perpendicular distance between two planes, both parallel with the reference plane, which encloses all points on the front surface of a wafer within the FQA, the site, or the sub site, depending on which is specified.
Total Thickness Variation (TTV)
The maximum variation in the wafer thickness. Total Thickness Variation is generally determined by measuring the wafer in 5 locations of a cross pattern (not too close to the wafer edge) and calculating the maximum measured difference in thickness.


Thin (thickness depends on wafer diameter, but is typically less than 1mm),circular slice of single-crystal semiconductor material cut from the ingot of single crystal semiconductor; used in manufacturing of semiconductor devices and integrated circuits; wafer diameters may range from 25mm to 300mm.
Wafer Bonding
Process in which two semiconductor wafers are bonded to form a single substrate; commonly applied to form SOI substrates; bonding of wafers of different materials, e.g. GaAs on Si, or SiC on Si; is more difficult than bonding of similar materials.
Wafer Diameter
The linear distance across the surface of a circular slice which contains the slice center and excludes any flats or other peripheral fiduciary areas. Standard silicon wafer diameters are: 25.4mm (1"), 50.4mm (2"), 76.2mm (3"), 100mm (4"), 125mm(5"), 150mm (6"), 200mm (8"), and 300mm (12").
Wafer Fabrication
Process in which a single crystal semiconductor ingot is fabricated and transformed by cutting, grinding, polishing, and cleaning into a circular wafer with a desired diameter and physical properties.
Wafer Flat
Flat area on the perimeter of the wafer; location and number of wafer flats contains information on crystal orientation of the wafer and the dopant type (n-type or p-type).
Deviation from a plane of a slice or wafer centerline containing both concave and convex regions.